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cortex-m-types
crate: standard traits and result handling for Cortex-M targets
#560
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Implementing |
CI failed because the ubuntu-latest label migrated to ubuntu 24.04 (https://github.blog/changelog/2024-09-25-actions-new-images-and-ubuntu-latest-changes/), and it looks like there the qemu package is no longer available. A quick fix would be to change the runner image to Alternatively, CI could use |
That was easier than I had expected: #562 |
Rebased and added |
CC @adamgreig Since this is replacing a previous PR from you. |
Hey @adamgreig could you take a quick look at this? I am planning to include a few suggestions from this PR to |
I'm very happy with the InterruptNumber trait and I think the additional traits are very sensible extensions too, no comments on them and definitely something I want before we release I'm not entirely sure of the utility of the new Error enum apart from giving us something to return from these traits. It otherwise feels quite generic and not really "cortex-m"-specific at all. I wonder if it should be tailored to be just the "error returned from these pac traits" instead of trying to be a more generically useful error. It reminds me a bit of having things like ValueError and KeyError in Python which are generally quite useful but not such a thing in Rust afaik. Finally I wonder if the name should be "cortex-m-pac-traits" instead of "cortex-m-pac". I always imagined "cortex-m-pac" would be a PAC for Cortex-M core peripherals/registers, using the same generator as other PACs to replace the current ad-hoc register access we have in the |
In RISC-V, we use this
I chose |
the same could be argued for |
Got it, so the utility is sharing it between
I get that, but it's still not itself a PAC, and everything else named |
Yes, The RISC-V PACs I know do not include the suffix |
I'd vote for calling this
I might make the same split for cortex-ar. |
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cortex-m-pac
crate: standard traits and result handling for Cortex-M targetscortex-m-types
crate: standard traits and result handling for Cortex-M targets
This PR ports some of the ongoing work in the RISC-V ecosystem to Cortex-M targets. Namely, I adapted the
riscv-pac
crate to the newcortex-m-pac
crate.The main purpose of this crate is to isolate fundamental traits and data types from potential breaking changes in
cortex-m
. Namely, it currently contains traits for enumerating exceptions, interrupts, priorities, and core IDs. It also provides a basic fallible function support for Cortex-M devices, with an error enum with some of the most typical issues developers may face.Related PRs in RISC-V: #222 and #223
Related PRs in Cortex-M: #488
Once this is merged, I plan to continue porting new functionalities from RISC-V to Cortex-M (e.g., new syntax for interrupt and exception macros)